The present invention is a method and apparatus for sampling high-speed electrical waveforms. Commercial and research demands for high-speed digital waveform acquisition and analysis have increased dramatically, outstripping current capability for measuring and processing such rapid streams of data. Digital signal analysis comprises sampling a time-varying waveform at discrete intervals, measuring those samples, either in voltage or current and processing the samples. With almost no exception, digital analysis requires samples taken at uniform time intervals; any non-uniformity results in undesirable spectral components centered around subharmonics of the sampling frequency. Since such distortions of the input data cannot be readily corrected, a useful sampler must offer some guarantee of performing uniform sampling of data.
At very high sampling rates, however, further processing of the data stream becomes difficult. Computational power ordinarily cannot keep up with signal frequencies in the gigahertz range. Slower processing requirements make some form of a rate reduction scheme inportant for a high-speed sampling system. Using several interleaved samplers, each sampler operating at a fraction of the overall system sampling frequency, one can achieve a high sampling rate while concurrently reducing each data stream rate to within conventional processing abilities. However, an interleaved sampling system magnifies the problem of timing uniformity error, due to the difficulty of accurately interleaving the separate sampling streams.
Using one first rank sample-and-hold circuit, implemented in Gallium Arsenide (Ga-As) bipolar technology, and demultiplexing its output into several second rank sample-and-hold circuits does offer uniform sampling and has been demonstrated at a 1 gigahertz sampling frequency. Poulton, Corcoran & Hornak, A 1 GHz 6-bit ADC System, SC-22 IEEE J. Solid-State Circuits No. 6, 962-970 (1987).
Charge-coupled devices allow sampling at even higher rates, higher than any other known electric circuit. However, further processing at this high rate again becomes extraordinarily difficult if not impossible, without some form of interleaving of samplers.
As discussed in Howes & Morgan, Charge-Coupled Devices and Systems, John Wiley & Sons, 1979, a charge-coupled device (CCD), in its simplest form, comprises an array of closely spaced Metal Oxide Semiconductor (MOS) capacitors. FIGS. 1 and 2 reveal a three-phase, two bit, n-channel CCD. The six MOS capacitors or electrodes connected to .phi..sub.1, .phi..sub.2, and .phi..sub.3 clock lines form the main body of the CCD while the input diode (ID), the input gate (IG), the output diode (OD), and the output gate (OG) form the input and output structure that injects and detects charge packets to and from the main CCD body. The p+ diffusion that surrounds the active area prevents a charge carrier inversion in the p-type silicon substrate. The device can be considered as a multi-gate MOS transistor.
The operation of the device can be explained with the aid the FIGS. 3 and 4, which show the various clock waveforms and the potential and charge distribution inside the device. At t=t.sub.1, .phi..sub.1 is at a high voltage (greater than the threshold voltage) while both .phi..sub.2 and .phi..sub.3 are at a low voltage. Both the input diode and the output diode are biased with high positive voltages to prevent the inversion of the surface under the input gate and the output gate. Therefore, the surfaces under the input and the output gates are in deep depletion and the input and the output diodes cannot supply electrons into the main CCD array. As a result, the six MOS capacitors are also in deep depletion and the surface potential is determined by the voltages applied to the electrodes. Surface potential is approximately linearly related to the gate voltage for an MOS capacitor in deep depletion with no mobile electrons at the surface. The surface potential under the .phi..sub.1 electrodes, therefore, will be higher than that under the .phi..sub.2 and .phi..sub.3 electrodes. If the distance between the electrodes, the gap length, is sufficiently small, the transition from the high surface potential under a .phi..sub.1 electrode to the low surface potential under a .phi..sub.2 or .phi..sub.3 electrode will be smooth. This creates energy wells under the .phi..sub.1 electrodes as shown in FIG. 4. If the device stays in this condition for a long time, thermally generated electrons will be collected in the energy wells, forming charge packets stored in confined regions under .phi..sub. 1 electrodes. In normal operation of a CCD, however, the clock frequency is sufficiently high for the number of thermally generated electrons to be negligible compared with the signal charge.
The signal charge is injected into the device at t=t.sub.2. At this time, the voltage of the input diode is lowered to a value between the surface potentials under the input gate and the .phi..sub.2 electrode. Electrons find regions of higher potential and flow into the energy well under the .phi..sub.1 electrode through the input gate. At the end of this injection, the surface potentials under the input gate and the first .phi..sub.1 electrode will be the same as the input diode voltage. Electrons are now stored under the input gate and the first .phi..sub.1 electrode.
At t=t.sub.3, the voltage of the input diode is returned to a high value and the electrons under the input gate as well as the excess electrons under the first .phi..sub.1 electrode will be taken out of the device through the input diode lead. This creates a well-defined charge packet under the first .phi..sub.1 electrode. The size of the charge packet is proportional to the difference between the surface potential under the input gate and that of the first .phi..sub.1 electrode. If the surface potential of the first .phi..sub.1 electrode is carefully controlled, its charge packet represents a sample corresponding to the input voltage applied to the Input gate.
At t=t.sub.4, the voltage applied to the .phi..sub.1 electrodes returns to the low value while the .phi..sub.2 electrodes have high voltage applied to them. The charge packet stored under the first .phi..sub.1 electrode moves to the first .phi..sub.2 electrode because the surface potential under the first .phi..sub.2 electrode is now higher. This process is called charge transfer. At t=t.sub.5, the charge-transfer process is completed and the charge packet is now stored under the first .phi..sub.2 electrode. This charge-transfer process is repeated and at t=t.sub.6, the injected charge packet is stored under the second .phi..sub.3 electrode. At t=t.sub.7, the voltage of the .phi..sub.3 electrodes returns to the low value and pushes the electron charge packet out to the output diode, providing an output signal proportional to the size of the charge packet and hence proportional to the input signal to the charge-coupled device.
While a charge-coupled device as described can comprise an extremely high speed digital sampling device, achieving sampling frequencies in excess of 1 gigahertz, no CCD device has demonstrated an interleaving of samples at such a high sampling rate. The electronic data acquisition and signal processing industry has faced a great challenge to produce a sampling circuit capable of both an extremely high base sampling frequency coupled with a method of interleaving separate samplers accurately, to reduce the rate for each separate data stream. The development of an improved data sampling circuit, capable of accurate interleaving at sampling rates in excess of one gigahertz, would represent a major technological advance. The precise and wide-bandwidth tracking of ultrahigh frequency signals such a sampler would allow would satisfy a long-felt need within the industry and offer to a large number of commercial and research users a versatile, faithful and inexpensive sampling and rate reduction circuit.